Senior Digital IC Verification Engineer

Job summary

This position involves verifying advanced System-on-Chip (SoC) designs for hearing aid technologies, focusing on ensuring the quality of future silicon platforms. The role includes hands-on verification, formal verification, and technical leadership within the verification team.

Qualifications

• Proven experience in digital IC verification.
• Proficient in SystemVerilog, UVM, and simulation-based verification.
• Familiarity with formal verification techniques is essential.
• Experience with SoC-level verification, coverage-driven verification, and Python scripting is highly desirable.
• Strong collaboration skills and ability to mentor junior engineers.

Responsibilities

• Define and execute verification strategies for digital IPs, subsystems, and SoCs.
• Develop UVM-based verification environments and conduct constrained-random testing.
• Perform coverage analysis and formal property development.
• Drive verification activities from planning through to sign-off.
• Mentor and provide technical guidance to less experienced engineers.
• Contribute to the continuous improvement of verification methodologies and best practices.

Skills

• Strong analytical and problem-solving skills.
• Excellent communication and teamwork abilities.
• Experience with automation scripting for verification processes.

Education

• Relevant degree in Electrical Engineering, Computer Engineering, or a related field.

Tools

• SystemVerilog, UVM, formal verification tools, simulation tools, and Python.